1. Field of the Invention
This invention relates to a digital-to-analog converter (hereinafter, termed "DAC") for use in PCM recording/playing apparatuses for video disks, video tapes etc., and more particularly to the circuit arrangement of a DAC with a compensating circuit which is suitable for fabrication in the form of an integrated circuit (IC).
2. Description of the Prior Art
Heretofore, there has been known a method wherein the nonlinear characteristics of a DAC are compensated for by employing a ramp voltage of good linearity as a linearity reference. In the method, the compensation is executed on the upper bits of a digital input having large linearity errors, and it is completed by storing compensation magnitudes for respective addresses into a RAM (Random Access Memory) while using the upper bits as the addresses. In case of operating the DAC for digital-to-analog conversion (DAC), the compensation magnitude is read out and is added to an input data in a digital or analog fashion. The method will be explained more concretely.
1 Case of Compensating Operation; A case of compensating for 4 upper bits of a digital input will be taken as an example.
A group of upper bits UB of a digital input and an output (initial value: "0000") of a first counter consisting of, for example, 4 bits are selected by a selecting circuit. At this time, a group of lower bits LB of the digital input are all made 0 (zero), and an output of a RAM or a group of compensation bits (consisting of m bits) is inhibited from entering. An input of the DAC consisting of the output of the selecting circuit and the lower bits LB is I.sub.o ="0000, 0 . . . 0," and an output of the DAC corresponding thereto includes only an offset component (e.sub.o volts). At the time when an output (V.sub.R volts) of a ramp voltage generator has exceeded e.sub.o volts, the counting of output clock pulses of a clock generator is started by a second counter (consisting of m bits). Simultaneously, an output (initial value: "0 . . . 0") of the second counter at this time is written into address "0000" of the RAM as a compensation magnitude for the input I.sub.o of the DAC, and the first counter counts up 1 (one) to make its output "0001."
Accordingly, the input of the DAC becomes I.sub.1 ="0001, 0 . . . 0." Letting e.sub.1 volts be the output of the DAC corresponding thereto, an output of the second counter at the time when the ramp voltage V.sub.R has exceeded e.sub.1 volts is written into address "0001" of the RAM as a compensation magnitude for the input I.sub.1 of the DAC, and the first counter counts up 1 (one) to make its output "0010."
Thereafter, compensation magnitudes for inputs (I.sub.2 -I.sub.15) of the DAC corresponding to outputs "0010"-"1111" of the first counter are similarly written into addresses "0010"-"1111" of the RAM, whereupon the compensating operations are completed.
2 Case of DAC Operation; The group of upper bits UB of the digital input are selected by the selecting circuit, they are applied to the DAC together with the group of lower bits LB and the output of the RAM corresponding to the upper bits UB, and a compensated analog output is provided.
According to the method described above in detail, one compensating operation requires a period of time of several tens of ms--several hundred ms, during which the DAC operation cannot be made. This brings about the problem that the DAC cannot be continuously used in such a case where the compensations need to be frequently made due to, for example, great temperature changes.